the aip74lvc1g74 is a single positive edge triggered d-type flip-flop with individual data (d) inputs, clock (cp) inputs, set (sd) and reset (rd) inputs, and complementary q andq outputs.
this device is fully specified for partial power-down applications using ioff. the ioff circuitry disables the output, preventing damaging backflow current through the device when it is powered down.
the set and reset are asynchronous active low inputs and operate independently of the clock input. information on the data input is transferred to the q output on the low-to-high transition of the clock pulse. the d inputs must be stable one set-up time prior to the low-to-high clock transition for predictable operation.
wide supply voltage range from 1.65v to 5.5v
5 v tolerant outputs for interfacing with 5 v logic
±24ma output drive (vcc=3.0v)
cmos low power consumption
latch-up performance exceeds 250ma
direct interface with ttl levels
input accepts voltages up to 5v
specified from -40℃ to 105℃
packaging information: tssop8/vssop8