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aip74hc/hct190
presettable synchronous bcd decade up/down counter

the aip74hc/hct190 are asynchronously presettable up/down bcd decade counters. they contain four

master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation.

asynchronous parallel load capability permits the counter to be preset to any desired number. information present on the parallel data inputs (d0 to d3) is loaded into the counter and appears on the outputs when the parallel load (pl()) input is low. as indicated in the function table, this operation overrides the counting function.

counting is inhibited by a high level on the count enable (ce()) input. whence() is low internal state changes are initiated synchronously by the low-to-high transition of the clock input. the up/down (u()/d) input signal determines the direction of counting as indicated in the function table. thece() input may go low when the clock is in either state, however, the low-to-highce() transition must occur only when the clock is high. also, theu()/d input should be changed only when eitherce() or cp is high.


  • 主要特点

  • 产品文档

  • input levels:

    for aip74hc190: cmos level

    for aip74hct190: ttl level

  • synchronous reversible counting

  • asynchronous parallel load

  • count enable control for synchronous expansion

  • single up/down control input

  • specified from -40℃ to 85℃

  • packaging information: dip16/sop16/tssop16


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