the aip74lvc573 consists of eight d-type transparent latches, featuring separate d-type inputs for each latch and 3-state true outputs for bus-oriented applications.
when le is high, data at the dn inputs enters the latches. in this condition, the latches are transparent, that is, a latch output changes each time its corresponding d-input changes. when le is low, the latches store the information that was present at the d-inputs one set-up time preceding the high-to-low transition of le.
inputs can be driven from either 3.3v or 5v devices. when disabled, up to 5.5v can be applied to the outputs. these features allow the use of these devices as translators in mixed 3.3v or 5v applications.
the aip74lvc573 is functionally identical to the aip74lvc373, but has a different pin arrangement.
5v tolerant inputs/outputs, for interfacing with 5v logic
supply voltage range from 1.2v to 3.6v
cmos low power consumption
direct interface with ttl levels
high-impedance when vcc=0v
flow-through pinout architecture
specified from -40℃ to 105℃